Advanced integrated circuit design requires precise control of beam incidence angles. While a number of different types of beam incidence angle error exist, three of the more common types are cone angle error, beam steering error and parallelism error across the wafer. Cone angle error is typically a result of cone angle effects caused by the geometry of the wafer scanning system. Cone angle error causes within wafer variation. For example the beam angle error may be about −x degrees at one edge of the wafer, be approximately zero degrees as the center of the wafer, and be about +x degrees at the opposing edge of the wafer.
Steering error, on the other hand, tends to be a fixed error across the wafer that is introduced while tuning the beam between lots, implant batches, or whenever the tuning may occur. The parallelism error, for whatever reason, leads to random beam incidence angle errors across the width of the wafer. This error is particularly difficult to correct as a result of its random nature.
Unfortunately, without precise control of beam incidence angles, various different problems degrade the transistors of the integrated circuit. As an example, transistor asymmetry, variation, and depressed MPY often result due to beam incidence angle error. The beam incidence angle error also typically leads to gate shadowing and an asymmetric dopant distribution, both of which are undesirable.
Turning to FIGS. 1A and 1B, illustrated is an example of an implant system 100 that could lead to gate shadowing on a transistor device. The implant system 100 illustrated in FIG. 1A includes one or more substrates 110 located on or over an implant platen 105. As is illustrated, a predominant axis of each of the substrates 110 is radial with respect to the implant platen 105. The radial nature of the substrates 105 in the example shown is accomplished by aligning an alignment feature 120 of the implant platen 105 with alignment features 125 on each of the substrates 110, the alignment features 125 on each of the substrates 110 aligned with a predominant axis of each of the substrates 110. The alignment features 120, 125, as one would expect, allow the substrates 110 to be easily positioned and aligned during an implant process.
Each of the substrates 110 theoretically have one or more transistor devices 140 located thereon that are being subjected to an implant process 130 as the implant platen 105 rotates. The transistor device 140 illustrated in FIG. 1B includes a gate structure 150, having a height (h), located over the substrates 110. The transistor device 140 illustrated in FIG. 1B is being subjected to the implant process 130 to form implant regions 160. As is illustrated, the combination of the implant beam incidence angle (θ) and gate structure 150 height (h) causes the implant regions 160 located within the substrates 110 not be placed equidistance from the gate structure 150. For example, one of the implant regions 160 is located a distance (d) from the sidewall of the gate structure 120, where the other implant region 160 is located adjacent the sidewall of the gate structure 150. While the distance (d) can be estimated using the equation d=h tan (θ), it nevertheless creates an undoped/underdoped region 170 defined by the distance (d) that often tends to cause serious operational problems for the transistor device 140.
Accordingly, what is needed in the art is a method for implanting dopants within a substrate that does not experience the drawbacks of the prior art methods and devices.